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1 lt1425 isolated flyback switching regulator n no transformer third winding or optoisolator required n 5% accurate output voltage without user trims (see circuit below) n resistor programmable output voltage n regulation maintained well into discontinuous mode (light load) n optional load compensation n operating frequency: 285khz n easily synchronized to external clock n available in 16-pin narrow so package features the lt ? 1425 is a monolithic high power switching regu- lator specifically designed for the isolated flyback topol- ogy. no third winding or optoisolator is required; the integrated circuit senses the isolated output voltage directly from the primary side flyback waveform. a high current, high efficiency switch is included on the die along with all oscillator, control and protection circuitry. the lt1425 operates with input supply voltages from 3v to 20v and draws only 7ma quiescent current. it can deliver output power up to 6w with no external power devices. by utilizing current mode switching techniques, it provides excellent ac and dc line regulation. the lt1425 has a number of features not found on other switching regulator ics. its unique control circuitry can maintain regulation well into discontinuous mode in most applications. optional load compensation circuitry allows for improved load regulation. an externally activated shut- down mode reduces total supply current to 15 m a for standby operation. descriptio n u typical applicatio n u + 11 isolated 9v 5% at 20ma to 200ma v 1425 ta01 *dale lpe 4841-330mb 12 5v d1 1n5819 500v isolation barrier t1* 15 6 4 3 r1 22.6k 1% 5 14 13 710 v in lt1425 sgnd pgnd v sw r fb r ref r ocomp shdn sync v c r ccomp r2 3.01k 1% r3 15k c4 0.1 m f c3 1000pf c1 100 m f 10v c2 47 m f 16v + f output current (ma) 0 output voltage (v) 8.5 9.0 8.9 8.8 8.7 8.6 9.5 9.4 9.3 9.2 9.1 50 100 1425 ta02 150 200 load regulation 5v to isolated C 9v out applicatio n s u n isolated flyback switching regulators n ethernet isolated 5v to C 9v converters n medical instruments n isolated telecom supplies , ltc and lt are registered trademarks of linear technology corporation.
2 lt1425 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u t jmax = 145 c, q ja = 75 c/ w top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd nc r fb v c r ref sync sgnd gnd gnd shdn r ocomp r ccomp v in v sw pgnd gnd order part number lt1425cs lt1425is electrical characteristics v in = 5v, t j = 25 c, v sw open, v c = 1.4v, unless otherwise specified. symbol parameter conditions min typ max units feedback amplifier i ref reference current measured at r fb pin with r ref = 3.000k 402 408 414 m a l 396 420 m a i in r ref pin input current 500 na g m feedback amplifier transconductance d i c = 10 m a (note 2) l 400 1000 1600 m mho i source , i sink feedback amplifier source or sink current l 30 50 80 m a v cl feedback amplifier clamp voltage 1.9 v reference voltage/current line regulation 5v v in 18v l 0.01 0.04 %/v voltage gain (note 3) 500 v/v v in sense error l 10 25 mv output switch bv output switch breakdown voltage i c = 5ma l 35 50 v v(v sw ) output switch on voltage i sw = 1a l 0.55 0.85 v i lim switch current limit duty cycle = 50%, 0 c t j 100 c l 1.35 1.60 1.9 a duty cycle = 50%, C 40 c t j 100 c l 1.25 1.60 1.9 a duty cycle = 80% 1.30 a current amplifier control pin threshold duty cycle = minimum 0.95 1.2 1.3 v l 0.85 1.4 v control voltage to switch transconductance 2 a/v timing f switching frequency 260 285 300 khz l 240 320 khz t on minimum switch on time 170 210 260 ns t ed flyback enable delay time 150 ns t en minimum flyback enable time 180 ns maximum switch duty cycle l 85 90 95 % consult factory for military grade parts. (note 1) supply voltage ........................................................ 20v switch voltage ......................................................... 35v shdn, sync pin voltage ........................................... 7v r fb pin current....................................................... 2ma operating junction temperature range commercial .......................................... 0 c to 100 c industrial ......................................... C 40 c to 100 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c
3 lt1425 electrical characteristics v in = 5v, t j = 25 c, v sw open, v c = 1.4v, unless otherwise specified. symbol parameter conditions min typ max units load compensation d v rccomp / d i sw 0.45 w sync function minimum sync amplitude l 1.5 2.2 v synchronization range 320 450 khz sync pin input resistance 40 k w power supply v in(min) minimum input voltage l 2.8 3.1 v i cc supply current l 7.0 9.5 ma shutdown mode supply current l 15 40 m a shutdown mode threshold l 0.4 0.9 1.3 v typical perfor m a n ce characteristics uw switch saturation voltage vs switch current temperature ( c) ?0 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 25 75 1425 g03 ?5 0 50 100 125 input voltage (v) switch current limit vs duty cycle minimum input voltage vs temperature switch current (a) 0 switch saturation voltage (v) 1.2 1.0 0.8 0.6 0.4 0.2 0 0.6 1.0 1425 g01 0.2 0.4 0.8 1.2 1.4 125 c 25 c ?5 c duty cycle (%) 0 switch current limit (a) 40 1425 g02 10 20 30 50 60 70 80 90 100 2.0 1.5 1.0 0.5 0 t a = 25 c the l denotes the specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: feedback amplifier transconductance is r ref referred. note 3: voltage gain is r ref referred.
4 lt1425 typical perfor m a n ce characteristics uw feedback amplifier output current vs r ref pin voltage r ref node voltage (v) 1.05 60 40 20 0 20 40 60 ?0 1.20 1.30 1425 g04 1.10 1.15 1.25 1.35 1.40 feedback amplifier output current ( a) 25 c 125 c ?5 c temperature ( c) ?0 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 25 75 1425 g06 ?5 0 50 100 125 v c pin voltage (v) v c high clamp v c threshold v c pin threshold and high clamp voltage vs temperature temperature ( c) ?0 1400 1200 1000 800 600 400 200 0 25 75 1425 g05 ?5 0 50 100 125 transconductance ( mho) error amplifier transconductance vs temperature (r ref referred) switching frequency vs temperature shdn pin input current vs voltage minimum synchronization voltage vs temperature temperature ( c) ?0 300 295 290 285 280 275 270 265 25 75 1425 g07 ?5 0 50 100 125 switching frequency (khz) temperature ( c) ?0 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 25 75 1425 g08 ?5 0 50 100 125 minimum synchronization voltage (v p-p ) shdn pin voltage (v) 0 1 0 ? ? ? ? 4 1425 g09 1 2 3 5 shdn pin input current ( a) t a = 25 c minimum switch on time vs temperature flyback enable delay time vs temperature temperature ( c) ?0 300 275 250 225 200 175 150 125 25 75 1425 g10 ?5 0 50 100 125 switch on time (ns) temperature ( c) ?0 250 225 200 175 150 125 100 75 25 75 1425 g11 ?5 0 50 100 125 enable delay time (ns) temperature ( c) ?0 275 250 225 200 175 150 125 100 25 75 1425 g12 ?5 0 50 100 125 enable time (ns) minimum flyback enable time vs temperature
5 lt1425 pi n fu n ctio n s uuu gnd (pins 1, 8, 9, 16): ground. these pins connect to the substrate of the die and are separate from the power ground and signal ground. they should connect directly to a good quality ground plane. r fb (pin 3): input pin for external feedback resistor connected to transformer primary (v sw ). the ratio of this resistor to the r ref resistor, times the internal bandgap (v bg ) reference, is the primary determinant of the output voltage (plus the effect of any nonunity transformer turns ratio). the average current through this resistor during the flyback period should be approximately 400 m a. see appli- cations information for more details. v c (pin 4): control voltage. this pin is the output of the feedback amplifier and the input of the current compara- tor. frequency compensation of the overall loop is effected by placing a capacitor between this node and ground. r ref (pin 5): input pin for external ground-referred reference resistor. this resistor should be in the range of 3k, but for convenience, need not be this value precisely. see applications information for more details. sync (pin 6): pin to synchronize internal oscillator to external frequency reference. it is directly logic compat- ible and can be driven with any signal between 10% and 90% duty cycle. if unused, this pin can be left floating; however, for best noise immunity the pin should be grounded. sgnd (pin 7): signal ground. this pin is a clean ground. the internal reference and feedback amplifier are referred to it. keep the ground path connection to r ref and the v c compensation capacitor free of large ground currents. pgnd (pin 10): power ground. this pin is the emitter of the power switch device and has large currents flowing through it. it should be connected directly to a good quality ground plane. v sw (pin 11): this is the collector node of the output switch and has large currents flowing through it. keep the traces to the switching components as short as possible to minimize electromagnetic radiation and voltage spikes. v in (pin 12): supply voltage. bypass input supply pin with 10 m f or more. the part goes into undervoltage lockout when v in drops below 2.8v. undervoltage lockout stops switching and pulls the v c pin low. r ccomp (pin 13): pin for the external filter capacitor for load compensation function. a common 0.1 m f ceramic capacitor will suffice for most applications. see applications information for further details. r ocomp (pin 14): input pin for optional external load compensation resistor. use of this pin allows nominal compensation for nonzero output impedance in the power transformer secondary circuit, including secondary wind- ing impedance, output schottky diode impedance and output capacitor esr. in less demanding applications this resistor is not needed. see applications information for more details. shdn (pin 15): shutdown. this pin is used to turn off the regulator and reduce v in input current to a few tens of microamperes. the shdn pin can be left floating when unused.
6 lt1425 block diagra m w flyback error a plifier diagra ww + d1 t1 isolated v out c1 + v in v sw v c c ext r fb r fb r ref r ref v bg q4 d2 q1 q2 q3 v in i i m i m i fxd enable 1425 ea + load compensation current amplifier driver logic 285khz oscillator 2.6v regulator shdn flyback error amplifier comp r ccomp r oc0mp r ref v sw r sense pgnd 1425 bd v c sgnd gnd is omitted for clarity v in r fb sync
7 lt1425 ti i g diagra w w u v sw voltage v in gnd off on minimum t on enable delay minimum enable time 1425 td off on switch state flyback amp state 0.80 v flbk v flbk collapse detect enabled disabled disabled operatio n u the lt1425 is a current mode switching regulator ic that has been designed specifically for the isolated flyback topology. the special problem normally encountered in such circuits is that information relating to the output voltage on the isolated secondary side of the transformer must be communicated to the primary side in order to maintain regulation. historically, this has been done with optoisolators or extra transformer windings. optoisolator circuits waste output power and the extra components they require increase the cost and physical volume of the power supply. optoisolators can also exhibit trouble due to limited dynamic response (temporal), nonlinearity, unit-to-unit variation and aging over life. circuits employing extra transformer windings also exhibit defi- ciencies. the extra winding adds to the transformers physical size and cost. dynamic response is often mediocre. there is usually no method for maintaining load regulation versus load. the lt1425 derives its information about the isolated output voltage by examining the primary side flyback pulse waveform. in this manner no optoisolator nor extra transformer winding is required. this ic is a quantum improvement over previous approaches because: target output voltage is directly resistor-programmable, regu- lation is maintained well into discontinuous mode and optional load compensation is available. the block diagram shows an overall view of the system. many of the blocks are similar to those found in tradi- tional designs including: internal bias regulator, oscilla- tor, logic, current amplifier and comparator, driver and output switch. the novel sections include a special flyback error amplifier and a load compensation mecha- nism. also, due to the special dynamic requirements of flyback control, the logic system contains additional functionality not found in conventional designs.
8 lt1425 operatio n u within the dashed lines in the block diagram can be found the r ref , r fb and r ocomp resistors. they are external resistors on the user-programmable lt1425. the capaci- tor connected to the r ccomp pin is also external. the lt1425 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier which derives its feedback informa- tion from the flyback pulse. due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. a good source of information on these topics is ltcs application note 19. error amplifierpseudo dc theory please refer to the simplified diagram of the flyback error amplifier. operation is as follows: when output switch q4 turns off, its collector voltage rises above the v in rail. the amplitude of this flyback pulse, i.e., the difference between it and v in , is given as: v flbk = v f = d1 forward voltage i sec = transformer secondary current esr = total impedance of secondary circuit n sp = transformer effective secondary-to-primary turns ratio v out + v f + (i sec )(esr) n sp the flyback voltage is then converted to a current by the action of r fb and q1. nearly all of this current flows through resistor r ref to form a ground-referred voltage. this is then compared to the internal bandgap reference by the differential transistor pair q2/q3. the collector current from q2 is mirrored around and subtracted from fixed current source i fxd at the v c pin. an external capacitor integrates this net current to provide the control voltage to set the current mode trip point. the relatively high gain in the overall loop will then cause the voltage at the r ref resistor to be nearly equal to the bandgap reference v bg . (v bg is not present in final output voltage setting equation. see applications information section.) the relationship between v flbk and v bg may then be expressed as: v flbk r fb v flbk = v bg a = ratio of q1 i c to i e v bg = internal bandgap reference a = or, r fb r ref v bg r ref ) ) 1 a ) ) combination with the previous v flbk expression yields an expression for v out , in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: v out = v bg ?v f ?i sec (esr) r fb r ref ) ) n sp a ) ) additionally, it includes the effect of nonzero secondary output impedance. see load compensation for details. the practical aspects of applying this equation for v out are found in the applications information section. so far, this has been a pseudo-dc treatment of flyback error amplifier operation. but the flyback signal is a pulse, not a dc level. provision must be made to enable the flyback amplifier only when the flyback pulse is present. this is accomplished by the dashed line connections to the block labeled enable. timing signals are then required to enable and disable the flyback amplifier. error amplifierdynamic theory there are several timing signals that are required for proper lt1425 operation. please refer to the timing diagram. minimum output switch on time the lt1425 effects output voltage regulation via flyback pulse action. if the output switch is not turned on at all, there will be no flyback pulse, and output voltage informa- tion is no longer available. this would cause irregular loop response and start-up/latchup problems. the solution chosen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. this in turn establishes a minimum load requirement to maintain
9 lt1425 operatio n u effects of variable enable period it should now be clear that the flyback amplifier is enabled only during a portion of the cycle time. this can vary from the fixed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. certain parameters of flyback amp behavior will then be directly affected by the variable enable period. these include effective transconductance and v c node slew rate. load compensation theory the lt1425 uses the flyback pulse to obtain information about the isolated output voltage. a potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. this has been represented previously by the expression (i sec )(esr). however, it is generally more useful to convert this expres- sion to an effective output impedance. because the sec- ondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the off duty cycle. that is, r out = esr where, r out = effective supply output impedance esr = lumped secondary impedance dc off = off duty cycle 1 dc off ) ) expressing this in terms of the on duty cycle, remember- ing dc off = 1 C dc, r out = esr dc = on duty cycle 1 1 ?dc ) ) in less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external r fb resistor value adjusted to compensate for nominal expected error. in more demanding applications, output impedance error regulation. see applications information section for fur- ther details. enable delay when the output switch shuts off, the flyback pulse appears. however, it takes a finite time until the trans- former primary side voltage waveform approximately rep- resents the output voltage. this is partly due to rise time on the v sw node, but more importantly due to transformer leakage inductance. the latter causes a voltage spike on the primary side not directly related to output voltage. (some time is also required for internal settling of the feedback amplifier circuitry.) in order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. this is termed enable delay. in certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. see applications information section for further details. collapse detect once the feedback amplifier is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, that compares the flyback voltage (r ref referred) to a fixed reference, nominally 80% of v bg . when the flyback waveform drops below this level, the feedback amplifier is disabled. this action accommodates both continuous and discontinuous mode operation. minimum enable time the feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed minimum enable time. this prevents lock-up, especially when the output voltage is abnormally low, e.g., during start-up. the mini- mum enable time period ensures that the v c node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. the minimum enable time often determines the low load level at which output voltage regulation is lost. see applications information section for details.
10 lt1425 operatio n u may be minimized by the use of the load compensation function. to implement the load compensation function, a voltage is developed that is proportional to average output switch current. this voltage is then impressed across the external r ocomp resistor and the resulting current is then sub- tracted from the r fb node. as output loading increases, average switch current increases to maintain rough output voltage regulation. this causes an increase in r ocomp resistor current subtracted from the r fb node, through which feedback loop action causes a corresponding increase in target output voltage. assuming a relatively fixed power supply efficiency, eff, power out = (eff)(power in) (v out )(i out ) = (eff)(v in )(i in ) average primary side current may be expressed in terms of output current as follows: i in = i out v out (v in )(eff) ) ) combining the efficiency and voltage terms in a single variable, i in = k1(i out ) where, k1 = v out (v in )(eff) ) ) switch current is converted to voltage by a sense resistor and amplified by the current sense amplifier with associ- ated gain g. this voltage is then impressed across the external r ocomp resistor to form a current that is subtracted from the r fb node. so the effective change in v out target is: d v out = k1( d i out ) r fb (r sense )(g) r ocomp ) ) expressing the product of r sense and g as the data sheet value of d v rccomp / d i sw , d v rccomp d i sw ) ) d v rccomp d i sw ) ) r fb r ocomp ) ) r out = k1 and, r fb r out ) ) r ocomp = k1 d v rccomp d i sw ) ) = data sheet value for r ccomp pin action vs switch current where, k1 = dimensionless variable related to v in , v out and efficiency as above r fb = external ?eedback?resistor value r out = uncompensated output impedance d v rccomp d i sw d v out d i out ) ) r fb r ocomp ) ) = k1 nominal output impedance cancellation is obtained by equating this expression with r out . the practical aspects of applying this equation to determine an appropriate value for the r ocomp resistor are found in the applications information section.
11 lt1425 applicatio n s i n for m atio n wu u u r ocomp , the external resistor value required for its nomi- nal compensation: 1 1 ?dc ) ) r out = esr d v rccomp d i sw ) ) r fb r out ) ) r ocomp = k1 while the value for r ocomp may therefore be theoretically determined, it is usually better in practice to employ empirical methods. this is because several of the required input variables are difficult to estimate precisely. for instance, the esr term above includes that of the trans- former secondary, but its effective esr value depends on high frequency behavior, not simply dc winding resis- tance. similarly, k1 appears to be a simple ratio of v in to v out times (differential) efficiency, but theoretically esti- mating efficiency is not a simple calculation. the sug- gested empirical method is as follows: build a prototype of the desired supply using the eventual secondary components. temporarily ground the r ccomp pin to disable the load compensation func- tion. operate the supply over the expected range of output current loading while measuring the output voltage deviation. approximate this variation as a single value of r out (straight line approximation). calculate a value for the k1 constant based on v in , v out and the measured (differential) efficiency. they are then com- bined with the data sheet typical value for ( d v rccomp / d i sw ) to yield a value for r ocomp . verify this result by connecting a resistor of roughly this value from the r ocomp pin to ground. (disconnect the ground short to r ccomp and connect the requisite 0.1 m f filter capacitor to ground.) measure the output impedance with the new compensation in place. modify the original r ocomp value if necessary to increase or decrease the effective compensation. once the proper load compensation resistor has been chosen, it may be necessary to adjust the value of the r fb resistor. this is because the load compensation system exhibits some nonlinearity. in particular, the circuit can shift the reference current by a noticeable selecting r fb and r ref resistor values the expression for v out developed in the operation section can be rearranged to yield the following expres- sion for r fb : v out + v f + i sec (esr) v bg )) ) ) r fb = r ref a n sp the unknown parameter a , which represents the fraction of r fb current flowing into the r ref node, can be repre- sented instead by specified data sheet values as follows: v bg (i ref )(3k) ) ) (i ref )( a )(3k) = v bg a = allowing the expression for r fb to be rewritten as: v out + v f + i sec (esr) i ref (3k)n sp ) ) r fb = r ref where, v out = desired output voltage v f = switching diode forward voltage (i sec )(esr) = secondary resistive losses i ref = data sheet reference current value n sp = effective secondary-to-primary turns ratio strictly speaking, the above equation defines r fb not as an absolute value, but as a ratio of r ref . so the next question is, what is the proper value for r ref ? the answer is that r ref should be approximately 3k. this is because the lt1425 is trimmed and specified using this value of r ref . if the impedance of r ref varies considerably from 3k, additional errors will result. however, a variation in r ref of several percent or so is perfectly acceptable. this yields a bit of freedom in selecting standard 1% resistor values to yield nominal r fb /r ref ratios. selecting r ocomp resistor value the operation section previously derived the following expressions for r out , i.e., effective output impedance and
12 lt1425 applicatio n s i n for m atio n wu u u amount when output switch current is zero. please refer to figure 1 which shows nominal reference current shift at zero load for a range of r ocomp values. example: for a load compensation resistor of 12k, the graph indi- cates a 1.0% shift in reference current. the r fb resistor value should be adjusted down by about 1.0% to restore the original target output voltage. integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting total turns and mutual inductance. turns ratio can then be chosen on the basis of desired duty cycle. however, remember that the input supply voltage plus the secondary-to-primary referred version of the flyback pulse (including leakage spike) must not exceed the allowed output switch breakdown rating. leakage inductance transformer leakage inductance (on either the primary or secondary) causes a spike after output switch turn-off. this is increasingly prominent at higher load currents where more stored energy must be dissipated. in many cases a snubber circuit will be required to avoid over- voltage breakdown at the output switch node. ltcs application note 19 is a good reference on snubber design. in situations where the flyback pulse extends beyond the enable delay time, the output voltage regulation will be affected to some degree. it is important to realize that the feedback system has a deliberately limited input range, roughly 50mv referred to the r ref node, and this works to the users advantage in rejecting large, i.e., higher voltage leakage spikes. in other words, once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. so the user is generally advised to arrange the snubber circuit to clamp at as high a voltage as comfortably possible, observing switch breakdown, such that leakage spike duration is as short as possible. as a rough guide, total leakage inductances of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. inductances from several percent up to perhaps ten percent cause increasing regulation error. severe leakage inductances in the double digit percentage range should be avoided if at all possible as there is a potential for abrupt loss of control at high load current. this curious condition potentially occurs when the leak- age spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback in less critical applications, or when output current remains relatively constant, the load compensation func- tion may be deemed unnecessary. in such cases, a reduced component solution may be obtained as follows: leave the r ocomp node open (r ocomp = ), and replace the filter capacitor normally on the r ccomp node with a short to ground. transformer design considerations transformer specification and design is perhaps the most critical part of applying the lt1425 successfully. in addi- tion to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should prove useful. turns ratio note that due to the use of an r fb /r ref resistor ratio to set output voltage, the user has relative freedom in selecting transformer turns ratio to suit a given application. in other words, screwball turns ratios like 1.736:1.0 can scru- pulously be avoided! in contrast, simpler ratios of small r ocomp (k w ) 1 d i ref (%) 2 10 100 1000 1425 f01 1 0 figure 1
13 lt1425 applicatio n s i n for m atio n wu u u degrades load regulation (at least before load compensa- tion is employed). bifilar winding a bifilar or similar winding technique is a good way to minimize troublesome leakage inductances. however, remember that this will increase primary-to-secondary capacitance and limit the primary-to-secondary break- down voltage, so bifilar winding is not always practical. finally, the ltc applications group is available to assist in the choice and/or design of the transformer. happy winding! output voltage error sources conventional nonisolated switching power supply ics typically have only two substantial sources of output voltage errorthe internal or external resistor divider network that connects to v out and the internal ic refer- ence. the lt1425, which senses the output voltage in both a dynamic and an isolated manner, exhibits additional potential error sources to contend with. some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. here is a list of possible error sources and their effective contribution: internal voltage reference the internal bandgap voltage reference is, of course, imperfect. its error, both at 25 c and over temperature is already included in the specifications for reference current. user programming resistors output voltage is controlled by the ratio of r fb to r ref . both are user supplied external resistors. to the extent that the resistor ratio differs from the ideal value, the output voltage will be proportionally affected. schottky diode drop the lt1425 senses the output voltage from the trans- former primary side during the flyback portion of the cycle. this sensed voltage therefore includes the forward drop, v f , of the rectifier (usually a schottky diode). the nominal signal! it then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. this will typically reduce the output volt- age abruptly to a fraction, perhaps between one-third to two-thirds of its correct value. if load current is reduced sufficiently, the system will snap back to normal opera- tion. when using transformers with considerable leakage inductance, it is important to exercise this worst-case check for potential bistability: 1. operate the prototype supply at maximum expected load current. 2. temporarily short circuit the output. 3. observe that normal operation is restored. if the output voltage is found to hang up at an abnormally low value, the system has a problem. this will usually be evident by simultaneously monitoring the v sw waveform on an oscilloscope to observe leakage spike behavior firsthand. a final note, the susceptibility of the system to bistable behavior is somewhat a function of the load i/v characteristics. a load with resistive, i.e., i = v/r behavior is the most susceptible to bistability. loads which exhibit cmossy, i.e., i = v 2 /r behavior are less susceptible. secondary leakage inductance in addition to the previously described effects of leakage inductance in general, leakage inductance on the second- ary in particular exhibits an additional phenomenon. it forms an inductive divider on the transformer secondary, that reduces the size of the primary-referred flyback pulse used for feedback. this will increase the output voltage target by a similar percentage. note that unlike leakage spike behavior, this phenomenon is load independent. to the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufac- turing variations), this can be accommodated by adjusting the r fb /r ref resistor ratio. winding resistance effects resistance in either the primary or secondary will act to reduce overall efficiency (p out /p in ). resistance in the secondary increases effective output impedance which
14 lt1425 applicatio n s i n for m atio n wu u u collapse, thereby supporting operation well into discon- tinuous mode. nevertheless, there still remain constraints to ultimate low load operation. they relate to the minimum switch on time and the minimum enable time. discontinu- ous mode operation will be assumed in the following theoretical derivations. as outlined in the operation section, the lt1425 utilizes a minimum output switch on time, t on . this value can be combined with expected v in and switching frequency to yield an expression for minimum delivered power. 1 2 ) ) f l pri ) ) min power = (v in ?t on ) 2 = (v out )(i out ) this expression then yields a minimum output current constraint: 1 2 ) ) f (l pri )(v out ) ) ) i out(min) = where, f = switching frequency (nominally 285khz) l pri = transformer primary side inductance v in = input voltage v out = output voltage t on = output switch minimum on time (v in ?t on ) 2 an additional constraint has to do with the minimum enable time. the lt1425 derives its output voltage infor- mation from the flyback pulse. if the internal minimum enable time pulse extends beyond the flyback pulse, loss of regulation will occur. the onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, t ed , plus the minimum enable time, t en . minimum power delivered to the load is then: 1 2 ) ) f l sec ) ) min power = [v out ?(t en + t ed )] 2 = (v out )(i out ) which yields a minimum output constraint: v f of this diode should therefore be included in r fb calculations. lot-to-lot and ambient temperature varia- tions will show up as output voltage shift/drift. secondary leakage inductance leakage inductance on the transformer secondary reduces the effective primary-to-secondary turns ratio (n p /n s ) from its ideal value. this will increase the output voltage target by a similar percentage. to the extent that secondary leakage inductance is constant from part-to- part, this can be accommodated by adjusting the r fb to r ref resistor ratio. output impedance error an additional error source is caused by transformer sec- ondary current flow through the real life nonzero imped- ances of the output rectifier, transformer secondary and output capacitor. because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the dc lumped secondary impedance times the inverse of the off duty cycle. if the output load current remains relatively constant, or, in less critical applications, the error may be judged acceptable and the r fb value adjusted for nominal expected error. in more demanding applications, output impedance error may be minimized by the use of the load compensation function (see load compensation). v in sense error the lt1425 determines the size of the flyback pulse by comparing the v sw signal to v in , through r fb . this comparison is not perfect, in the sense that an offset exists between the sensing mechanism and the actual v in . this is expressed in the data sheet as v in sense error. this error is fixed in absolute millivolt terms relative to v out (with the exception that it is reflected to v out by any nonunity secondary-to-primary turns ratio). minimum load considerations the lt1425 generally provides better low load perfor- mance than previous generation switcher/controllers utilizing indirect output voltage sensing techniques. specifically, it contains circuitry to detect flyback pulse
15 lt1425 applicatio n s i n for m atio n wu u u minimum switch on time, irrespective of current trip point. if the duty cycle exhibited by this minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current will not be controlled at the nominal value, and will cycle-by-cycle ratchet up to some higher level. expressed mathematically, the requirement to maintain short-circuit control is: v f + (i sc )(r sec ) (v in )(n sp ) ) ) (t on )(f) < where, t on = output switch minimum on time f = switching frequency i sc = short-circuit output current v f = output diode forward voltage at i sc r sec = resistance of transformer secondary v in = input voltage n sp = secondary-to-primary turns ratio (n sec /n pri ) trouble will typically only be encountered in applications with a relatively high product of input voltage times secondary-to-primary turns ratio. additionally, several real world effects such as transformer leakage inductance, ac winding losses and output switch voltage drop com- bine to make this simple theoretical calculation a conser- vative estimate. in cases where short-circuit protection is mandatory and this theoretical calculation indicates cause for concern, the prototype should be observed directly as follows: short the output while observing the v sw signal with an oscilloscope. the measured output switch on time can then be compared against the specifications for minimum t on . thermal considerations care should be taken to ensure that the worst-case input voltage and load current conditions do not cause exces- sive die temperatures. the narrow 16-pin package is rated at 75 c/w. 1 2 ) ) f(v out ) l sec ) ) i out(min) = where, f = switching frequency (nominally 285khz) l sec = transformer secondary side inductance v out = output voltage t ed = enable delay time t en = minimum enable time (t ed + t en ) 2 note that generally, depending on the particulars of input and output voltages and transformer inductance, one of the above constraints will prove more restrictive. in other words, the minimum load current in a particular applica- tion will be either output switch minimum on time constrained, or minimum flyback pulse time constrained. (a final notel pri and l sec refer to transformer induc- tance as seen from the primary or secondary side respec- tively. this general treatment allows these expressions to be used when the transformer turns ratio is nonunity.) maximum load/short-circuit considerations the lt1425 is a current mode controller. it uses the v c node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. the internal clamp on the v c node, nominally 1.9v, then acts as an output switch peak current limit. this action becomes the switch current limit specification. the maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. short-circuit conditions are handled by the same mecha- nism. the output switch turns on, peak current is quickly reached and the switch is turned off. because the output switch is only on for a small fraction of the available period, internal power dissipation is controlled. (the lt1425 contains an internal overtemperature shutdown circuit, that disables switch action, just in case.) while the majority of users will not experience a problem, there is however, a possibility of loss of current limit under certain conditions. remember that the lt1425 exhibits a
16 lt1425 applicatio n s i n for m atio n wu u u average supply current (including driver current) is: i sw 35 ) ) i in = 7ma + dc where, i sw = switch current dc = on switch duty cycle switch power dissipation is given by: p sw = (i sw ) 2 (r sw )(dc) r sw = output switch on resistance total power dissipation of the die is the sum of supply current times supply voltage plus switch power: p d(total) = (i in ? v in ) + p sw frequency compensation loop frequency compensation is performed by connect- ing a capacitor from the output of the error amplifier (v c pin) to ground. an additional series resistor, often required in traditional current mode switcher controllers is usually not required, and can even prove detrimental. the phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a zero to the loop response. in further contrast to traditional current mode switchers, v c pin ripple is generally not an issue with the lt1425. the dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the v c voltage changes during the flyback pulse, but is then held during the subsequent switch on portion of the next cycle. this action naturally holds the v c voltage stable during the current comparator sense action (current mode switching). pcb layout considerations for maximum efficiency, switch rise and fall times are made as short as practical. to prevent radiation and high frequency resonance problems, proper layout of the com- ponents connected to the ic is essential, especially the power paths (primary and secondary). b field (magnetic) radiation is minimized by keeping output diode, switch pin and output bypass capacitor leads as short as possible. e field radiation is kept low by minimizing the length and area of all traces connected to the switch pin. a ground plane should always be used under the switcher circuitry to prevent interplane coupling. the high speed switching current paths are shown sche- matically in figure 2. minimum lead length in these paths are essential to ensure clean switching and minimal emi. the path containing the input capacitor, transformer pri- mary, output switch, the path containing the transformer secondary, output diode and output capacitor are the only ones containing nanosecond rise and fall times. keep these paths as short as possible. high frequency circulating path v out v in high frequency circulating path isolated load 1425 f02 f figure 2
17 lt1425 typical applicatio n s u the following are several application examples of the lt1425. the first shows an isolated lan supply which provides C 9v with 1% load regulation for output cur- rents of 0ma to 250ma. an alternate transformer, the coiltronics part, provides a complete pcmcia type ii height solution. the lt1425 offers excellent load regula- tion and fast dynamic response not found in similar isolated flyback schemes. the next example shows a 15v supply with 1.5kv of isolation. the sum of line/load/cross regulation is better than 3%. full load efficiency is between 72% (v in = 5v) and 80% (v in = 15v). the isolation is ultimately limited only by bobbin selection and transformer construction. the C 48v to 5v isolated telecom supply uses an external cascoded 200v mosfet to extend the lt1425s 35v maximum switch voltage limit. the input voltage range (C 36v to C 72v) also exceeds the lt1425s 20v maximum input voltage, so a bootstrap winding is used. d1, d2, q2 and q3 and associated components for the necessary start-up circuitry with hysteresis. when c1 charges to 15v, switching begins and the bootstrap wind- ing begins to supply power before c1 has a chance to discharge to 11v. feedback voltage is fed directly through a resistor divider to the r ref pin. the load compensation circuitry is bypassed, resulting in 5% load regulation. finally, the 12v to 5v isolated converter is similar to the previous example in that a cascoded mosfet is used to prevent voltage breakdown of the output switch. but because the nominal 12v input is well within the range of the v in pin, no bootstrap winding is required and normal load compensation function is provided. diode d1, tran- sistor q1 and associated components provide an under- voltage lockout function via the shdn pin. the off-the- shelf transformer provides up to 5w of isolated regulated power. C 9v isolated lan supply transformer t1 lpri ratio isolation (l w h) i out efficiency d1 d2 r1, r2 c5, c6 r3 dale lpe-4841-a307 36 m h 1:1:1 500vac 10.7 11.5 6.3mm 250ma 76% not used not used 47 w 330pf 13.3k coiltronics ctx02-13483 27 m h 1:1 500vac 14 14 2.2mm 200ma 70% 1n5248 mbr0540tl1 75 w 220pf 5.9k 1424/25 ta03 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd nc r fb v c r ref sync sgnd gnd 3.01k 1% r3 r1 r2 2 4 1 3 7 mbrs130lt3 t1 6 22.1k 1% 0.1 m f lt1425 47pf c5 c6 c3 10 m f 25v c4 10 m f 25v 1.8k out com ?v 1000pf c1 10 m f 25v 5v input com c2 10 m f 25v 0.1 m f 100k gnd shdn r ocomp r ccomp v in v sw pgnd gnd c1, c2, c3, c4 = marcon thcs50e1e106z ceramic capacitor, size 1812. (847) 696-2000 d1 d2
18 lt1425 typical applicatio n s u 15v isolated power supply + + + 1425 ta04 lt1425 mbrs1100t3 mbrs1100t3 4 5 6 7 t1* 3 2 18 gnd nc r fb v c r ref sync sgnd gnd gnd shdn r ocomp r ccomp pin 3 to 4, 7 turns bifilar 34awg *philips efd-15-3f3 core gap for primary l = 40 m h 0.12 inch margin tape pin 7 to 8, 28 turns 40awg pin 5 to 6, 28 turns 40awg pin 1 to 2, 7 turns bifilar 34awg 3 layers 2 mil polyester film v in v sw pgnd gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 3.01k 1% 1n759 18.4k 0.1% 3k 15v 60ma ?5v 60ma out com 7.32k 1% 75 w 5v to 15v input com 0.1 m f 220pf 1 m f 22 m f 35v 15 m f 35v 3k 15 m f 35v 1000pf 0.1 m f 130 w 330pf 9 mbr0540lt1 + + + 1425 ta06 bav21 bav21 mur120 lt1425 5k 18 w mbr745 10 w 4 7 8 t1* 3 2 1 gnd nc r fb v c r ref sync sgnd gnd gnd shdn r ocomp r ccomp v in v sw pgnd gnd 1 2 3 4 5 6 7 8 16 t1 6 5 15 14 13 12 11 10 3.16k 1% q2 2n3906 q3 2n3904 q1 irf620 d1 7.5v 1n755 d2 7.5v 1n755 30.1k 1% r2 18 w r1 24k 50 w 1w 510 w 10k 2.4k 100k input com ?6v to ?2v 3.3 m f 150pf 0.1 m f 0.1 m f c1 27 m f 35v 150 m f 6.3v 150 m f 6.3v 5v 2a out com 1000pf 470pf 9 pin 3 to 4, 15 turns bifilar 31awg *philips efd-15-3f3 core gap for primary l = 100 m h pin 7 to 8, 6 turns quadfilar 29awg pin 5 to 6, 15 turns bifilar 33awg pin 1 to 2, 15 turns bifilar 31awg 1 layer 2 mil polyester film 2 layers 2 mil polyester film C 48v to 5v isolated telecom supply
19 lt1425 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio n u dimensions in inches (millimeters) unless otherwise noted. s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 0695 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
20 lt1425 1425fa lt/tp 1198 2k rev a ? printed in usa ? linear technology corporation 1997 typical applicatio n u 12v to 5v isolated converter related parts part number description comments lt1105 off-line switching regulator built-in isolated regulation without optoisolator ltc ? 1145/46 isolated digital data transceivers up to 200kbps data rate, ul listed lt1170/71/72 5a/3a/1.25a flyback regulators isolated flyback mode for higher currents lt1372/77 500khz/1mhz boost/flyback regulators uses ultrasmall magnetics lt1424 application specific isolated regulator 8-pin fixed voltage version of lt1425 + + + 220 m f 10v 1425 ta05 lt1425 mbrs340t3 2 5 1 4 6 3 10 7 11 8 12 9 gnd nc r fb v c r ref sync sgnd gnd gnd shdn r ocomp r ccomp v in v sw pgnd gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 3.01k 1% 25.5k 1% 9.3k 1% mmft1n10e 2.4k 12v input com 0.1 m f 22 m f 35v 220 m f 10v 200 w 5v 1a out com coiltronics vp1-0190 turns ratio 1 : 1 : 1 : 1 : 1 : 1 12 m h per winding 407-241-7876 1000pf 1000pf mur120 q1 2n3906 0.1 m f 100 w 10 w 1.8k 330pf 9 d1 1n755 7.5v linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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